스텝시스템

Buyer Inform Auto Import Load & Design Rule Check Tool Operation(Self-Development) Technique

Self-developed design verification program to supplement items that are incapable of checking in the DRC(Design Rule Check)

Main Fuction

>> DATA ANALYSYS

DESIGN DATA
- CHIP PARTS / POWER / FSOURCE POWER / SITE(DUT) / COMPONENT RELAY / CARD RELAY (EDS) /
  Forced connected to DCIO / CBIT Division Circuit / SUB SOCKET / LEVEL SHIFTER / SPI ROM

>> DESIGN RULE CHECK

COMMON
- CHANNEL OPEN / CHANNEL Duplicated / NC Duplicated
DIGITAL SIGNAL
- NET NAME RULE / "P_" NET Assign Check / DIFFERENTIAL PAIR / SLOT / SCAN CHAIN / BUYER OPTION
ANALOG SIGNAL
- ANALOG RELAY / T2000 ANALOG RULE / BUYER OPTION
POWER SIGNAL
- EDS Power Connection / RELAY Power Connection / POWER INFORMATION / POWER GANG / SITE(DUT) Power Connection /
  SITE(DUT) GND Connection / POWER CHANNEL Connection / BUYER OPTION
RELAY CBIT
- CBIT Connection / CBIT OPEN / CBIT Duplicated / CBIT Division Circuit / CBIT MERGE Check / DUMMY RELAY
ETC
- Relay Net Connection / Parts Placement / Ball Assign / Design Mother / U-FLEX XD SLOT / U-FLEX HEXVS SLOT

>> LENGTH CHECK

>> DATA REPORT

DATA IMPORT TYPES

Types	Description
IMPORT DATA	Data drawn up based on the production request sheet information
DESIGN DATA	Net information designed with Allegro
LENGTH DATA	Length data of the net designed with Allegro
BOM DATA	Information data of parts designed with Allegro

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